TCP/IP stack in hardware with SME

Since FPGA's are very low level and have been difficult to work with, many components that a software programmer takes for granted are not readily available. Most components require a setting up a royalty-based licensing deal, making it difficult to approach for academics and experimental development. With the SME model we want to make "hardware development for software programmers" and as part of that we would like to have a working TCP stack implemented in SME. This would be a full stack working with real wire signals, implementing all layers described in RFC 1122. Ideally, the implementation will provide a "TCP offload engine" (ToE) that provides an ordered stream of data to another circuit on the FPGA. For Bachelor projects and smaller projects, it would be useful to implement just one or two of the layers (either link+IP or IP+TCP).

Tags: sme hardware fpga tcp ip network

Activities: Implement a TCP/IP stack in SME such that it can run on an FPGA

Contact: Kenneth Skovhede <>, Brian Vinter <>

Area: Masters