RISC-V in SME

RISC-V is a new open architecture; the home-page says: ”RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.” The project will be to design a structure for a RISC-V and implement a subset of the processor in SME.

Tags: SME:Hardware

Activities: Design and programming.

Contact: Brian Vinter, vinter@nbi.ku.dk or Kenneth Skovhede, skovhede@nbi.ku.dk

Area: Masters